First it’s important to note, Verilog code is generally not executable on its own.
A few common run-times execute it in different modes.
The first (and foremost) run-time we’ll examine is event-driven simulation.
In such simulations, most procedural blocks are not explicitly called.
They are instead triggered by events occurring elsewhere in the simulated hardware.
The languages include keywords for common trigger-events such as:Beginning of simulation (initial)On change of a particular signal (always)On changes of rising/ falling edge polarity (posedge, negedge)And several more.
This discrete-event representation is sufficiently general to capture nearly all practical digital chip design.
GitHub holds a few such examples, such as the PicoRV32 RISC-V CPU, and Western Digital’s Swerve CPU cores.
module RISCVCPU (clock); // A RISC-V module excerpt parameter LD = 7'b000_0011, // Instruction opcodes SD = 7'b010_0011, BEQ = 7'b110_0011, NOP = 32'h0000_0013, ALUop = 7'b001_0011; input clock; reg [63:0] PC; // .
integer i; initial begin for (i=0; i<=31; i=i+1) Regs[i] = i; endalways @(posedge clock) begin // Fetch & increment PC IFIDIR <= IMemory[PC >> 2]; PC <= PC + 4; IDEXA <= Regs[IFIDrs1]; IDEXB <= Regs[IFIDrs2]; // .
end // .
endmoduleA typical HDL simulator runs an event-loop, processing these events in order, and adding new ones as procedural blocks, logical and arithmetic operations, and signal assignments generate them.
In a future article we will explore the mechanics of these event-based simulation runtimes.
A second critical run-time for the C-like HDLs is logic synthesis.
This is effectively the compiler for digital chip design.
A typical synthesis program takes two primary inputs: the HDL source code, and library information on the available logic gates in the target technology.
This second runtime introduces a fairly significant difference between HDLs and their software brethren: many HDL programs which can be run, can’t be compiled.
HDLs include the notion of a synthesizable subset of constructs, which can be converted into gate-level netlists.
Most event-driven procedural blocks, such as that of RISCVCPU above, can generally be synthesized.
Other test-focused constructs such as initial are limited to simulation.
In future posts we'll explore the verification-focused features of SystemVerilog, which include a far richer programmer's feature-set, at the expense of not being able to synthesize hardware.
High-Level Hardware LanguagesAbove this C(ish) level, hardware languages diverge (even further) by domain.
High level models mean very different things to different engineers.
Large systems-on-chip benefit from transaction-level models, often composed in SystemC.
Special-purpose circuits are often designed in similarly special-purpose analytical models, often designed in conventional programming languages, or graphical tools such as Simulink.
High-level synthesis refers to a category of tools which generate hardware descriptions from algorithmic descriptions of what the hardware should do, leaving out many of the hardware-description details such as modules, ports, and signals.
often written in C++ and similar languages.
These tools attempt to abstract away many of the details of the hardware (clocks, resets, and the like), without materially expanding the programming-language feature set.
(Typical programs would be a restricted subset of C or C++.
)The FutureThe primary trend in new HDLs, particularly those from academia, is to instead create a hardware description library, embedded inside an existing high-level programming language.
Chisel, written in Scala and designed tightly in conjunction with RISC-V, is probably the most prominent example.
Engineers at Google and other large companies have detailed their experience using this relatively new tool-chain.
Notably, Chisel and comparable libraries do not attempt high-level synthesis; they instead primarily focus on the structural model, and embed its construction in the productivity-focused features of its high-level programming language.
The picture we’ve laid out here came together over a long time.
Software engineering moves a mile a minute; seemingly every week a new tool, framework, or language has risen to popularity, and another has fallen in its place.
Verilog, in contrast, was introduced in 1984, and remains industry-standard today.
Hardware folks move cautiously.
But there is reason to believe this space is ripe for change.
The next generation of hardware — both the companies and the engineers — will come from the software space, with very different attitudes about moving quickly, adopting new productivity technologies, and sharing them.